This application relates in general to VLSI design and in specific to a method used to estimate the resistance and capacitance values associated with signal routing and interconnects between blocks in a VLSI design before the actual layout and route is completed.
In a large scale VLSI design project, the initial step is to create a description of what the chip is going to do. This description is created in Register Transfer Language (xe2x80x9cRTLxe2x80x9d). One of the design considerations in a chip layout is to optimize the RC values of the configuration and minimize the negative effects that the RC values may have on timing. Connection paths for signals between different blocks of the chip have inherent RC values that may cause delays in propagation. According to known methods, the RC values have been either ignored completely or approximated by considering only a capacitance component at the initial description stage of a VLSI design project. This was acceptable because RC delays are typically low compared to gate delays. According to one prior method, the resistive component could be disregarded at the initial layout stage and the total line capacitance is just lumped. In the past, this produced a fair estimation. Another method was to explicitly place RC""s in the schematics. This involved roughly planning out where various blocks would be placed. The length of the wire may be measured in order to derive the resistance and capacitance on a wire or path so that it may be added to a schematic layout. This process made it difficult to consider the RC values as components were moved or different configurations were explored, because the values needed to be recalculated.
The initial design was an RTL phase with a program defining the chip functions. Next was a schematic phase which arranged gates and other components in a schematic. Finally, there was the layout phase. The RTL phase did not give consideration to RC values. The schematic phase would try to incorporate some RC values such as lump capacitance, consider certain limited RC elements or completely ignore RC values. Traditional RC values were not considered until the artwork phase or layout phase of the project. At that point tools would extract the actual RC elements and a timing model could evaluate how fast the chip could be run and evaluate the impact of RC delay. The drawback to this methodology is that the design effort was relatively far along before RC delays were considered, making it very difficult to revise the design to overcome the negative impact of such RC delays.
It is an object of the invention to overcome these and other disadvantages in the prior art. It is an object to provide a methodology to consider RC values at an earlier stage of the VLSI chip design in order to facilitate optimization, thereby minimizing delays. It is an object to provide a methodology to facilitate VLSI chip design, which permits higher operating speeds. It is a further object of the invention to consider RC delays at an earlier stage of the VLSI design process. It is a further object to create VLSI chips designed according to an advanced methodology which considers RC delays at an early stage of the design process.
These and other objects, features and technical advantages are achieved by a system and method as described herein.
According to a feature of the invention, a tool is provided to perform RC estimation at the RTL design phase. Early in a design project a floor planning tool may be used to obtain a rough composition or prediction of the proposed chip layout, including port and component and block placement. An RC estimation tool may then estimate a port to port route and estimate the chip topology for the route and derive RC values. The tool may then build a net list specifying connections and including RC values in a timing model. This permits a timing analysis early in the design project. According to the invention, both the resistive and the capacitive characteristics of the signal paths may be incorporated into the timing model. This avoids the approximations inherent in ignoring the RC values or lumping the capacitance.
One advantage according to the invention is that the RC is distributed in the model which models the characteristics of real silicon more realistically than a lump capacitance. According to the invention, optimization of RC characteristics is much easier to accomplish with a design tool at an early stage than it was at a later stage with estimated explicit RC""s in a schematic. The use of a design tool permits a process that allows reconfiguration of route topology, metal space, width and coupling coefficients. It also permits variations of components and geography that affect the RC characteristics.
One advantage of the use of a methodology or protocol according to the invention is the facilitation of use of data hierarchically. A tool permits analysis at a block level and then establishment of a composition of multiple blocks, in a hierarchical manner. It may be advantageous to permit establishment of 20 or more layers in such a hierarchy. One advantage of the invention is the ability to explore many layout options without changing hard coded RC values in the schematic. This facilitates quickly moving blocks around and re-estimating the signal path routing to determine timing. This is an advance over the prior methodology which required manual estimation of signal path propagation delays. One advantage is that the net list outputs may be in the same format as used for full extraction design tools. This facilitates use of the net list and RC timing model by all other tools used in the VLSI design process.
According to an advantageous feature of the invention, a method may be provided suitable for VLSI chip design. The features relate primarily to the initial stages of the design and facilitate early consideration of resistive and capacitive characteristics of signal paths. The method may include the steps of estimating signal routes between functional blocks, optionally followed by the step of foliating nodes in the estimated signal routes. An advantageous feature includes determining resistance and capacitive values for the estimated signal routes and may include building a model of said signal paths, including the resistance and capacitive values. Advantageously, the method may include the step of generating a connectivity net list from the model. This step of estimating may be performed based on an input of a floor plan, a connectivity description, and manual or physical configuration parameters. The estimation process may also be controlled by a number of factors, including specification of signal routing algorithms. The configuration information may vary over the length of a signal path or vary for the routes between various nodes. Likewise, the resistance and capacitance values ascertained during the step of determining may be broken down for portions of the signal route and need not be lumped approximations for the entire route. The step of determining RC values may be done by a look-up table. The look-up table process may use interpolation to arrive at a more accurate estimation for data points falling between entries in the table. Alternatively, the step of determining RC values may be performed by direct and actual calculations.
The invention also encompasses chips manufactured after being designed by the afore described process.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.